1. Technical Field
The present invention relates in general to the field of computers, and, in particular, to computer processors. Still more particularly, the present invention relates to an improved method and system for determining a cause for an execution delay for an instruction or a group of instructions in the computer processor.
2. Description of the Related Art
Modern computer processors are capable of processing multiple instructions simultaneously through the use of multiple execution units within the processor, resulting in the completion of one or more instructions every clock cycle. Performance analysis of the processor requires the detection of conditions that prevent instructions from completion. Instructions may not be able to be completed for a variety of reasons, including data cache misses (waiting for data from memory or higher level cache memory), data dependency (waiting for the output of a previous instruction) and execution delays (time required to execute an instruction that has the required data).
In many modem computer processors, instructions are loaded into the processor within a group of instructions. The total number of groups of instructions can exceed several thousand. To optimize performance of the computer processor, causes for delays to instruction completions in the computer processor need to be determined. Determining these causes for execution completion delays is especially difficult when evaluating a group of instructions, since each instruction within the group may be delayed for multiple reasons.
Thus, there is a need for a method and system for identifying and evaluating causes of instruction completion delays for groups of instructions being processed by the computer processor, in order to provide needed information for improving the efficiency of the processor.